\[ \textbf{Question: } \text{In an instruction execution pipeline, the earliest that the instruction TLB and data TLB can be accessed are:} \] \[ \begin{array}{ll} \textbf{A.} & \text{Fetch stage and memory stage respectively} \\[6pt] \textbf{B.} & \text{Memory stage and execute stage respectively} \\[6pt] \textbf{C.} & \text{Memory stage and memory stage respectively} \\[6pt] \textbf{D.} & \text{Fetch stage and fetch stage respectively} \end{array} \] --- \[ \textbf{Explanation:} \] - **Instruction TLB (I-TLB):** Needed during the \emph{instruction fetch stage}, since the virtual instruction address must be translated to a physical address before fetching from memory. - **Data TLB (D-TLB):** Needed during the \emph{memory stage}, when load/store instructions access memory and require address translation. --- \[ \boxed{\text{Correct Answer: A. Fetch stage and memory stage respectively}} \]